According to Tesla's latest artificial intelligence accelerator roadmap disclosed via Tom's Hardware, the company has restarted its Dojo D3 training chip with a redesigned architecture and introduced performance targets for its next-generation inference processors. D3 will adopt a chiplet design integrating 2.5D and 3D packaging technologies with stacked high-bandwidth memory (HBM), replacing the previous SRAM-centric approach used in earlier generations.

Tesla's sixth-generation inference accelerator SI6 is projected to deliver 80x greater computational performance than the current fourth-generation HW4 chip, with computing power estimated between 17.28 and 46.08 POPS. SI6 will use 2-nanometer process technology under a partnership with Samsung extending through 2033, with an expected launch window of 2029 to 2030. Memory capacity is projected at 144GB, compared to 16GB in HW4. The company has rebranded its AI accelerator line as "Super Intelligence" (SI) series, renaming earlier generations accordingly.

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